HMS30C7110 Datasheet, PDF (99/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
Table 2.57 IER Bit Definition
Address : 1800_0004
Bits Access Default Description
31:4
0x00 Reserved
3
RW 0x0 MODEM Status Interrupt Enable
When set to logic 1 this bit enables the MODEM Status Interrupt
2
RW 0x0 Receiver Line Status Interrupt Enable
When set to logic 1 this bit enables the Receiver Line Status
Interrupt.
1
RW 0x0 Transmitter Holing Register Empty Interrupt Enable
When set to logic 1 this bit enables the Transmitter Holding Register
Empty Interrupt.
0
RW 0x0 Receive Data Available Interrupt Enable
When set to logic 1 this bit enables the Receive Data Available
Interrupt and Timeout Interrupt in the FIFO Mode.
2.7.2.4. Interrupt Identification Register (IIR)
In order to provide minimum software overhead during data character transfers, each serial channel
of the UART prioritizes interrupts into four levels and records these in the Interrupt Identification
Register. The four levels of interrupt conditions in order of priority are Receiver Line Status;
Received Data Ready; Transmitter Holding Register Empty; and MODEM Status.
Table 2.58 IIR Bit Definition
Address : 1800_0008
Bits Access Default Description
31:4
0x00 Reserved
3
RO 0x0
This bit is set along with bit 2 when a timeout interrupt is pending.
2:1 RO 0x00 These two bits of the IIR identify the highest priority interrupt
pending from those shown in Table 2.64.
© 2003 MagnaChip Semiconductor Ltd. All Rights Reserved
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