HMS30C7110 Datasheet, PDF (33/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
cacheable area.
Table 2.2 System Memory Map : SDRAM_REMAP = 0
Base Address
0x3e00_0000
0x3c00_0000
0x3800_0000
0x3000_0000
0x2c00_0000
0x2800_0000
0x2400_0000
0x2000_0000
0x1960_0000
0x1950_0000
0x1948_0000
0x1940_0000
0x1930_0000
0x1920_1000
0x1920_0000
0x1910_0000
0x1908_0000
0x1900_0000
0x1860_0000
0x1850_0000
0x1840_0000
0x1830_0000
0x1820_0000
0x1810_0000
0x1808_0000
0x1800_0000
0x1000_0000
0x0800_0000
0x0200_0000
0x0100_0000
0x0000_0000
Size
32MB
32MB
64MB
128MB
64MB
64MB
64MB
64MB
106MB
1MB
0.5MB
0.5MB
1MB
996KB
4KB
1MB
0.5MB
0.5MB
10MB
1MB
1MB
1MB
1MB
1MB
0.5MB
0.5MB
128MB
128MB
96MB
16MB
16MB
Function
CardBus special cycle
CardBus configuration
CardBus I/O
CardBus memory
Reserved
Attribute memory of PCMCIA
Common memory of PCMCIA
I/O area of PCMCIA
Reserved
CACHE registers
CardBus Bridge registers
PCMCIA Interface registers
INTC registers
ENET MAC1 registers
ENET MAC0 registers
DMA registers
SDRAMC registers
ROMC registers
Reserved
Reserved
SPI registers
WDT/CLKRST registers
GPIO registers
TIMER registers
UART1 registers
UART0 registers
SDRAM memory
Reserved
Reserved
Flash/IO/SRAM bank-1
Flash/IO/SRAM bank-0
© 2003 MagnaChip Semiconductor Ltd. All Rights Reserved
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Version 1.5