HMS30C7110 Datasheet, PDF (47/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
2.3.2. User Accessible Registers (Base = 0x1830_0000)
This section describes the registers in the Clock Module. The address value on the table shows the
relative address in hexadecimal. The width describes the number of bits in the register. The access
field specifies the valid access type for the register, where ‘RW’ stands for read and writes access,
and ‘RO’ for read only access, respectively. ‘C’ following ‘RW’ or ‘RO’ means the corresponding
bit is cleared after writing “1” in the matching position.
Table 2.7 Registers for PLL & Watchdog Timer
Name
PLL Enable
WDT control
WDT interval
Main PLL Control
PLL Reset
Address
0x00
0x04
0x08
0x0c
0x10
Width
32
32
32
32
32
Access
RW
RW
RW
RW
R
Description
Enable for PLL clocks
Control for watch dog timer
Time interval for watch dog timer
Control for main PLL
Status of PLL
2.3.2.1. PLL Enable
This register is used to select internal three clocks between external low frequency clock and
internal PLL output clock.
Table 2.8 PLL control
Address : 1830_0000
Bits Access Default Description
31:4
0x00 Reserved
3
RW 0x1
Bus Clock Ratio vs. CPU clock. SCLK is from the Bus Clock.
0 = Bus Clock is Divided by 2 from CPU clock
1 = Bus Clock is delibered directly from CPU clock
2:1
0x0 Reserved
© 2003 MagnaChip Semiconductor Ltd. All Rights Reserved
47
Version 1.5