HMS30C7110 Datasheet, PDF (95/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
2.7. UART
The HMS30C7110® integrates a serial interface which supports Universal Asynchronous Receiver /
Transmitter (UART) function. It is compatible with the NS16550A.
The universal asynchronous receiver / transmitter supports independent 1 channel Tx/Rx
functionality. The UART supports full duplex and it has 16 bytes internal FIFOs to overcome
interrupt latency for receiving and sending data.
The serial information exchanged between host PC and serial device has a synchronization bit (start
of frame), stop bit (end of frame) and error detection bit (parity bit). The supported parity is even,
odd, forced one, and forced zero.
The UART is designed to clear the cumulative clock jitter between host PC and UART device.
When the UART detects the start bit, the clock generator synchronize internal counter to the falling
edge of start bit. For this reason, the maximum tolerable jitter rate is 5 % of BAUD rate.
The UART contains following features.
z Full duplex
z Receive FIFO of 16 bytes
z 6, 7 or 8 bits per character
z 1 or 2 stop bits
z Odd parity, even parity, forced parity or none
z Break detection and generation
z Parity, overrun and framing error detection
z Receiver timeout interrupt
z Programmable BAUD rate generator
z Two modem control signals
z Auto-flow control
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