HMS30C7110 Datasheet, PDF (129/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
This register is used to mask the requests of some interrupt sources. If a bit of the register is set to 1,
it indicates that the corresponding interrupt is disabled. If it is set to 0, the corresponding interrupt
will be serviced normally. This mask register actually resides after the SRCPND register and affects
the effective value of SRCPND register going to arbitration logic and NMI generation logic.
Therefore, even for the masked requests, SRCPND register reflects their arrival as usual.
Interrupt Sources
Interrupt controller supports 21 interrupt sources as shown in the below table.
Table 2.96 Interrupt Source Register
Sources
INT_UART1
INT_UART0
INT_SPI
Reserved
CardBus
CARD IRQ
PCMCIA
INT_GPIO
INT_DMA1
INT_DMA0
INT_ENET1
INT_ENET0
INT_TIMER
INT_EXT7
INT_EXT6
INT_EXT5
INT_EXT4
INT_EXT3
INT_EXT2
INT_EXT1
Bit
29
28
27
26
22
21
20
19
18
17
14
11
10
7
6
5
4
3
2
1
Descriptions
Arbiter Group
UART1 interrupt
ARB5
UART0 interrupt
ARB5
SPI interrupt
ARB4
Reserved
ARB4
CardBus error interrupt
ARB4
IRQ from installed Card
ARB3
PCMCIA interrupt including card ARB3
detection
GPIO interrupt (from GPI8 ~ GPI10) ARB3
DMA channel 1 interrupt
ARB3
DMA channel 0 interrupt
ARB3
ENET MAC 1 interrupt
ARB2
ENET MAC 0 interrupt
ARB2
TIMER interrupt
ARB2
External interrupt 7 (from GPI7)
ARB1
External interrupt 6 (from GPI6)
ARB1
External interrupt 5 (from GPI5)
ARB1
External interrupt 4 (from GPI4)
ARB1
External interrupt 3 (from GPI3)
ARB0
External interrupt 2 (from GPIO2)
ARB0
External interrupt 1 (from GPIO1)
ARB0
© 2003 MagnaChip Semiconductor Ltd. All Rights Reserved
129
Version 1.5