HMS30C7110 Datasheet, PDF (110/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
Table 2.70 Timer Control Register Bit Definition
Address : 1810_0004
Bits Access Default Description
31:10
Reserved
9
W
0
Timer 2 clear
Writing ‘1’ to this bit clears the channel 2 counter.
8
RW 0
Timer 2 enable
0 = Timer2 disable
1 = Timer2 enable
7: 6
Reserved
5
W
0
Timer 1 clear
Writing ‘1’ to this bit clears the channel 1 counter.
4
RW 0
Timer 1 enable
0 = Timer1 disable
1 = Timer1 enable
3: 2
Reserved
1
W
0
Timer 0 Clear
Writing ‘1’ to this bit clears the channel 0 counter.
0
RW 0
Timer 0 enable
0 = Timer0 disable
1 = Timer0 enable
2.8.1.3. Timer Interval 0~2
These registers include timer values.
Table 2.71 Timer Interval Register Bit Definition
Address : 1810_0008, 1810_000C, 1810_0010
Bits Access Default Description
31: 0 RW 0
INTERVAL
This 32-bit field contains the interval value that is loaded to the down
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