HMS30C7110 Datasheet, PDF (70/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

MRXD[3:0] 4
I
MRXERR 1
I
MCOLL
1
I
MCRS
1
I
MDC
MDIO
1
I
1
I/O
HMS30C7110
prior to the first MRXCLK that follows the final nibble.
Receive Data Nibble. Signals are the receive data nibble. They
are synchronized to the rising edge of MRXCLK. When
MRXDV is asserted, the PHY sends a data nibble to the RX
MAC. For a correctly interpreted frame, seven bytes of a
preamble and a completely formed SFD must be passed across
the interface. If 7-wire interface is selected, MRXD[0] will carry
data bits, all others will be unused.
Receive Error. PHY asserts this signal to indicate to the RX
MAC that a media error was detected during the transmission of
the current frame. MRXERR is synchronous to the MRXCLK
and is asserted for one or more MRXCLK clock periods and
then deasserted.
Collision Detected. The PHY asynchronously asserts the
collision signal MCOLL after the collision is detected on the
media. When deasserted, no collision is detected on the media.
Carrier Sense. The PHY asynchronously asserts the carrier sense
MCRS signal after the medium is detected in a non-idle state.
When deasserted, signal indicates that the media is in the idle
state (and the transmission can start).
Management Data Clock. Clock for the MDIO serial data
channel.
Management Data Input/Output. Bi-directional serial data
channel for PHY/STA communication.
PHY Interface Signals
2.6.2. User Accessible Registers (Base = 0x1920_0000)
This section describes registers inside the Ethernet MAC. The address field in the following table
indicates an address offset in hexadecimal from Ethernet Base Address defined in the CPU section.
Width specifies the number of bits in the register and access specifies the valid access types of the
register. Where ‘RW’ stands for read and write access, ‘RO’ for read only access. A ‘C’ indicates
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