HMS30C7110 Datasheet, PDF (116/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
Table 2.80 The Bit Definition of the Interrupt Enable Register
Bits
31: 16
15: 0
Access
RW
Default
0x00
0x00
Description
Reserved
INT ENABLE
This 16-bits field enables the GPI interrupts.
0 = disable
1 = enable
Address : 1820_0010
2.9.1.6. INT MODE
The interrupt mode register chooses the interrupt mode of either level trigger or edge trigger.
Table 2.81 Interrupt Mode Register Bit Definition
Bits
31: 16
15: 0
Access
RW
Default
0x00
0x00
Address : 1820_0014
Description
Reserved
INT MODE
This 16-bits field controls the interrupt mode of each GPI pins.
0 = Level trigger
1 = Edge trigger
2.9.1.7. INT LEVEL
The interrupt level register selects active level of interrupt sources when in level triggering mode,
active low or active high.
Table 2.82 Interrupt Level Register Bit Definition
Bits Access Default Description
Address : 1820_0018
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