HMS30C7110 Datasheet, PDF (120/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

2.10.2.1. SPI Control (offset = 0x00)
This register includes SPI enable bit and baud rate setting value.
HMS30C7110
Table 2.84 SPI Control Register Bit Definition
Bits Access Default Description
31:9
0
Reserved
8
RW 0
Enable
0 = SPI clock disable
1 = SPI clock enable
7:0 RW 0
Baud rate
One clock period = (baudrate+1) × CLKIN
Address : 1840_0000
2.10.2.2. SPI Mode 0 (offset = 0x04)
These registers include recovery cycle field and data width field.
Table 2.85 Configuration Register Bit Definition
Address : 1840_0004
Bits Access Default Description
31:12
0
Reserved
7:4 RW 0
Recovery time
This 4-bit field is used for making recovery time from one access
cycle to the next access cycle.
3:1
0
Reserved
0
RW 0
Tx Start
This one bit field is used to start transfer of Tx FIFO data.
2.10.2.3. TX Data (offset = 0x18)
This register is writing path to 32 bytes Tx FIFO.
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