HMS30C7110 Datasheet, PDF (62/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

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27:24
23:21
20
19:16
15:13
12: 0
HMS30C7110
0x1 Clock Select for SDRAM Read.
1 : Clock Source = SCLK output
0 : Clock Source = MCLK input
0x3 Delay for SDRAM Read Clock (0-15ns).
0x0 Reserved.
0x0 Clock Select for SDRAM Write.
1 : Clock Source = SCLK output
0 : Clock Source = MCLK input
0x3 Delay for SDRAM Write Clock (0-15ns).
0x0 Reserved
0x0 Refresh Interval
This 13-bit field is used to enable refresh and set the refresh period.
When set to zero, refresh cycles are disabled. When set to non-zero,
refresh cycles are enabled, and are requested internally based on this
programmed value. RP and RC control the timing waveform of refresh
cycle. This field is set to zero on the hard reset, so refreshes are disabled
after a hard reset. This field is a one-based number, and is programmed
in CLK period.(1/CLK)
t_REFINT = (REFINT + 1) /CLK
2.5.2.4. INIT Control
This register includes init bit.
Table 2.19 INIT Control register
Address : 1908_0018
Bits Access Default Description
31:1
Reserved.
0
WO 0
INIT
This bit when set invokes an SDRAM power up initialization sequence.
All other fields in this register must be programmed with valid values
before or at the same time init is set. Once the initialization sequence is
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