HMS30C7110 Datasheet, PDF (81/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

Bits Access Default Description
31:0 RW 0x0 Transmit buffer start address
HMS30C7110
2.6.2.7. TX_LENGTH (offset = 0x18)
The total frame length (starting from destination address to the end of frame, excluding CRC field)
should be written to this register.
Table 2.29 Transmit Buffer Length
Bits Access Default Description
31:16 RW 0x00 Reserved
15:0 RW 0x00 Transmit buffer length in bytes
MAC0 Address : 1920_0018
MAC1 Address : 1920_1018
2.6.2.8. RX_BADDR (offset = 0x1C)
The starting address of RX buffer to store incoming frame is written to this register. RX_BADDR
can hold 15 entries of the start address of RX buffer. The number of entries not taken for RX
processing can be read from bits[10:8] of RX_BUFLVL (offset = 0x24). Not assigning a buffer
address in time will result in an interrupt (if enabled) with INT_SRC bit[5] and the frame will be
dropped.
Table 2.30 Receive Buffer Address
Bits Access Default Description
31:0 RW 0x00 Receive buffer start address
MAC0 Address : 1920_001C
MAC1 Address : 1920_101C
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