HMS30C7110 Datasheet, PDF (105/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
received character did not have a valid Stop bit. The FE bit is set to
logic 1 when the serial channel detects logic 0 during the first Stop
bit time. The FE indicator is reset whenever the CPU reads the
contents of the Line Status Register. This error is associated with the
particular character in the FIFO it applies to. This error is revealed to
the CPU when its associated character is at the top of the FIFO.
2
RO 0x0 Parity Error (PE)
This bit is the Parity Error (PE) indicator. Bit 2 indicates that the
received data character does not have the correct even or odd parity.
This error is associated with the particular character in the FIFO it
applies to. This error is revealed to the CPU when its associated
character is at the top of the FIFO.
1
RO 0x0 Overrun Error (OE)
This bit is the Overrun Error indicator. Bit 1 indicates that the next
character received was transferred into the Receiver Buffer Register
before the CPU could read the previously received character. It is
reset whenever the CPU reads the contents of the Line Status
Register.
0
RO 0x0 Data Ready (DR)
This bit is the receive Data Ready indicator. Bit 0 is set to logic 1
whenever a complete incoming character has been received and
transferred into the Receiver FIFO. Bit 0 is reset to logic 0 by
reading all of the data in the Receive FIFO.
2.7.2.9. MODEM Status Register (MSR)
This register provides the current stat of the control lines from the MODEM. Details on each bit
follow:
Table 2.65 MSR Bit Definition
Bits Access Default Description
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Address : 1800_0018
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