HMS30C7110 Datasheet, PDF (104/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
2.7.2.8. Line Status Register (LSR)
The Register provides status information to the CPU concerning the data transfer. Details on each
bit follow:
Table 2.64 LSR Bit Definition
Address : 1800_0014
Bits Access Default Description
31:8
0x00 Reserved
7
RO 0x0 FIFO error
This bit is set when there is at least one parity error, framing error or
break indication if the FIFO. It is cleared when the CPU reads the
LSR, if there are no subsequent errors in the FIFO.
6
RO 0x0 Transmitter Empty (TEMT)
This bit is the Transmitter Empty indicator. Bit 6 is set to logic 1
whenever the transmitter FIFO and shift register are both empty.
5
RO 0x0 Transmitter Holding Register Empty (THRE)
This bit is the Transmitter Holding Register Empty indicator. this bit
is set when the XMIT FIFO is empty; it is cleared when at least 1
byte is written to the XMIT FIFO.
4
RO 0x0 Break Interrupt (BI)
This bit is the Break Interrupt indicator. Bit 4 is set to logic 1
whenever the received data input is held in the Spacing (logic 0)
state for longer than a full word transmission time. The BI indicator
is reset whenever the CPU reads the contents of the Line Status
Register or when the next valid character is loaded into the Receiver
FIFO. This error is associated with the particular character in the
FIFO it applies to. This error is revealed to the CPU when its
associated character is at the top of the FIFO. When break occurs
only one zero character is loaded into the FIFO.
3
RO 0x0
Framing Error (FE)
This bit is the Framing Error indicator. Bit 3 indicates that the
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