HMS30C7110 Datasheet, PDF (76/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

7
0
6
RW 0
5
RW 0
4
RW 0
3
RW 0
2
RW 0
1
RW 0
0
RW 0
HMS30C7110
Reserved
1 = RX frame cut due to bus busy & excessive incoming frames
1 = RX frame dropped due to no buffer assigned.
1 = RX completed.
1 = SYS RX FIFO overflow
1 = SYS RX FIFO underflow
1 = MAC RX FIFO overflow
1 = MAC RX FIFO underflow
2.6.2.3. INT_ENABLE (offset = 0x08)
Each bit of this register can be set to enable corresponding interrupt source. Writing ‘0’ disables the
source from generating interrupt.
Table 2.25 Interrupt Enable Bit Definition
MAC0 Address : 1920_0008
MAC1 Address : 1920_1008
Bits Access Default Description
31 RW 0
MII PHY
0 = Interrupt disabled
1 = Interrupt enabled
This bit will be set whenever PHY device sends an interrupt
30 RW 0
MII Scan
0 = Interrupt disabled
1 = Interrupt enabled
This bit will be set when single read is completed in scan mode. Refer to
MII_CMD register (offset = 0x34).
29 RW 0
TX error occurred at PHY
0 = Interrupt disabled
1 = Interrupt enabled
28 RW 0
RX error occurred at PHY
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