HMS30C7110 Datasheet, PDF (103/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
2.7.2.7. MODEM Control Register (MCR)
This register controls the interface with the MODEM or data set. Details on each bit follow:
Table 2.62 MCR Bit Definition
Address : 1800_0010
Bits Access Default Description
31:6
0x00 Reserved
5
RW 0x0 AUTOFLOW
When this bit is set, the auto-flow control is enabled. The auto-flow
control can be configured by setting bit 1 and 5 of MCR as shown in
Table 2.68.
4
RW 0x0 LOOPBACK Enable
This bit provides a local loop-back feature for diagnostic testing of
the associated serial channel.
3:2
0x00 Reserved
1
RW 0x0 RTS Control
This bit controls the Request to Send (RTS#) output. Bit 1 affects the
RTS# output in a manner identical to that described below for bit 0.
0
RW 0x0 DTR Control
This bit controls the Data Terminal Ready (DTR#) output. When bit
0 is set to logic 1, the DTR# output is forced to a logic 0. When bit 0
is reset to logic 0, the DTR# output is forced to logic 1.
Table 2.63 Autoflow Control Configuration
Bit5 Bit1
1
1
1
0
0
X
Description
Auto-rts and auto-cts enabled
Auto-cts only enabled
Auto-rts and auto-cts disabled
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