HMS30C7110 Datasheet, PDF (147/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
2.13.1.15. Command for CardBus
Table 2.120 Command Bit Definition
Address : 1948_0000
Bits Access Default Description
31:9
0x0 Reserved
9
RO 0x0
Fast back to back enable
This 1 bit field is fixed to “0” because the bridge doesn’t support fast
back to back transaction.
8
RW 0x0
CSERR enable
This 1 bit field is used for enabling nCSERR pin interrupt.
7
RW 0x0
Wait cycle control (No connection to actual block)
This 1 bit field is fixed to “0” because the bridge doesn’t support this
function.
6
RW 0x1
Parity error response
This 1 bit field is used for enabling nCPERR pin interrupt.
5
RO 0x0
VGA pallet snoop enable
This 1 bit field is fixed to logic 0 because the bridge doesn’t support
this functionality.
4
RO 0x0
Memory write invalidate enable
This 1 bit field is used for enabling MWI and MRL command.
3
RO 0x0
Special cycle monitoring enable
This 1 bit field is fixed to logic 0 because the bridge doesn’t support
this functionality.
2
RO 0x1
Bus mastering enable
This 1 bit field is fixed to logic 1 because the bridge always supports
the master functionality.
1
RO 0x1
Memory access enable
This 1 bit field is fixed to logic 1 because the bridge always supports
the memory area accessing.
© 2003 MagnaChip Semiconductor Ltd. All Rights Reserved
147
Version 1.5