HMS30C7110 Datasheet, PDF (60/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

10 = 10-bit column width
11 = Reserved
15:14
0x0 Reserved
13: 8 RW 0x0 START ADDRESS (Reserved for future usage)
7: 6
0x0 Reserved
5: 0 RW 0x3f END ADDRESS (Reserved for future usage)
HMS30C7110
2.5.2.2. Timing
This register includes the timing information for all banks.
Table 2.17 Timing register
Address : 1908_0010
Bits Access Default Description
31 WO 0x0 NOP
When writing 1 at this bit, it will make NOP command to SDRAM
30:28 RW 0x7 TMODE (Mode Register Set to Active Delay)
This 3-bit field specifies the number of cycles guaranteed between mode
register set command at the end of the initialization sequence and the
first activate command.
27
0x0 Reserved.
26:24 RW 0x7 DPL (Write to Pre-charge Delay)
This 3-bit field specifies the number of cycles guaranteed between write
command and a pre-charge command.
23
0x0 Reserved.
22:20 RW 0x7 RCD (RAS to CAS Delay)
This 3-bit field specifies the number of cycles between RAS and CAS.
19
0x0 Reserved
18:16 RW 0x7 RP (Row Pre-charge Time)
This 3-bit field specifies the number of cycles needed for the pre-charge
command. A RP value of zero results in a RAS pre-charge of two clocks,
as if RP was selected to 1.
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