HMS30C7110 Datasheet, PDF (132/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
set to 1 if the corresponding interrupt source generates the interrupt request and waits for the
interrupt to be serviced. By reading this register, we can see the interrupt sources waiting for their
requests to be serviced. Note that each bit of SRCPND register is automatically set by the interrupt
sources regardless of the masking bits in the INTMASK register. In addition, it is not affected by
the priority logic of interrupt controller.
In the interrupt service routine for a specific interrupt source, the corresponding bit of SRCPND
register has to be cleared to get the interrupt request from the same source correctly. If you return
from the ISR (interrupt service routine) without clearing the bit, interrupt controller operates as if
another interrupt request comes in from the same source. In other words, if a specific bit of
SRCPND register is set to 1, it is always considered as a valid interrupt request waiting to be
serviced.
The specific time to clear the corresponding bit depends on the user's requirement. The bottom line
is that if you want to receive another valid request from the same source you should clear the
corresponding bit first, and then enable the interrupt.
You can clear a specific bit of SRCPND register by writing a data to this register. It clears only the
bit positions of SRCPND corresponding to those set to one in the data. The bit positions
corresponding to those that are set to 0 in the data remains as they are with no change.
Register Address
SRCPND 0x00
Table 2.97 Source Pending Register
Address : 1930_0000
R/W Description
value
R/W 0 = The interrupt has not been requested
0x00000000
1 = The interrupt source has asserted the interrupt
request
Bit
Field
Bit
Field
Bit
31
Reserved
23
Reserved
15
30
Reserved
22 INT_CARDBUS 14
29 INT_UART1 21 INT_PCMIRQ 13
28 INT_UART0 20 INT_PCMCIA 12
27
INT_SPI
19
INT_GPIO
11
26
Reserved
18
INT_DMA1
10
25
Reserved
17
INT_DMA0
9
Field
Reserved
INT_ENET1
Reserved
Reserved
INT_ENET0
INT_TIMER
Reserved
© 2003 MagnaChip Semiconductor Ltd. All Rights Reserved
132
Bit
Field
7 INT_EXT7
6 INT_EXT6
5 INT_EXT5
4 INT_EXT4
3 INT_EXT3
2 INT_EXT2
1 INT_EXT1
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