HMS30C7110 Datasheet, PDF (61/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

15:12 RW 0xf
11: 8 RW 0xf
7: 6
0x0
5: 4 RW 0x7
3: 2
0x0
0
RW 0x1
HMS30C7110
RAS (Row Active Time)
This 4-bit field specifies the number of cycles guaranteed between an
activate command and a pre-charge command.
RC (Row Cycle Time)
This 4-bit field specifies the number of cycles for a refresh command. It
also specifies the number of cycles between bank activation commands
to the same bank.
Reserved
CL (CAS Latency)
This value is used to program the SDRAM devices during the
Initialization sequence, and internally by the SDRAM controller.
0 = 1 clock
1 = 2 clocks
2 = 3 clocks
3 = Reserved
Reserved
Row Hit Enable
This value is used to enable the checking of the row address from
internal logic matched with row address of destination SDRAM. It may
cause one or two clock delay in accessing SDRAM but will make sure
that correct operation will be happening.
0 : Do not check whether row address is HIT or not.
1 : Check whether row address is HIT or not.
2.5.2.3. Refresh Interval
This register includes refresh interval value and MCLK tuning control reginter.
Table 2.18 Refresh Interval
Bits Access Default Description
31:29
0x0 Reserved.
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61
Address : 1908_0014
Version 1.5