HMS30C7110 Datasheet, PDF (69/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
Below Table show the PHY interface I/O signals
Port
Width Direction Description
MTXCLK 1
I
Transmit Nibble or Symbol Clock. The PHY provides the
MTXCLK signal. It operates at the frequency of 25MHz
(100Mbps) or 2.5MHz (10Mbps). The clock is used as a timing
reference for the transfer of MTXD[3:0], MTXEN, and
MTXERR.
MTXD[3:0] 4
O
Transmit Data Nibble. Signals are the transmit data nibble. They
are synchronized to the rising edge of MTXCLK. When
MTXEN is asserted, PHY accepts the MTXD. If 7-wire
interface is selected, MTXD[0] will carry data bits, all others
will be tri-stated.
MTXEN 1
O
Transmit Enable. When asserted, signal indicates to the PHY
that the data MTXD[3:0] is valid and the transmission can start.
Then transmission starts with the first nibble of the preamble.
Signal remains asserted until all nibbles to be transmitted are
presented to the PHY. It is deasserted prior to the first MTXCLK
following the final nibble of a frame.
MTXERR 1
O
Transmit Coding Error. When asserted for on e MTXCLK clock
period while MTXEN is also asserted, it causes the PHY to
transmit one or more symbols that are not part of the valid data
or delimiter set somewhere in the frame being transmitted to
indicate that there has been a transmit coding error.
MRXCLK 1
I
Receive Nibble or Symbol Clock. The PHY provides the
MTXCLK signal. It operates at the frequency of 25MHz
(100Mbps) or 2.5MHz (10Mbps). The clock is used as a timing
reference for the reception of MRXD[3:0], MRXDV and
MRXERR.
MRXDV 1
I
Receive Data Valid. The PHY asserts this signal to indicate to
the RX MAC that it is presenting the valid nibbles on the
MRXD[3:0] signals. Signal is asserted synchronously to the
MRXCLK. MRXDV is asserted from the first recovered nibble
of the frame to the final recovered nibble. It is then deasserted
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