HMS30C7110 Datasheet, PDF (148/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
0
RO 0x1
IO access enable
This 1 bit field is fixed to logic 1 because the bridge always supports
the I/O area accessing.
2.13.1.16. Status for CardBus
This register will be cleared when it is read.
Table 2.121 Status Bit Definition
Address : 1948_0004
Bits Access Default Description
31:16
0x0 Reserved
15 RO 0x0 Detected parity error
This 1 bit field is set when nCPERR pin is asserted.
14 RO 0x0 Received system error
This 1 bit field is set when nCSERR pin is asserted.
13 RO 0x0 Received master abort
This 1 bit field is set when the bridge get the master abort signaling
from the PC card.
12 RO 0x0 Received target abort
This 1 bit field is set when the bridge get the target abort signaling
from the PC card.
11 RO 0x0 Signaled target abort
This 1 bit field is set when the bridge make a target abort signaling.
10 RO 0x1 DEVSEL timing
This 1 bit field is fixed to 0x1 and that means the bridge operates as
a medium slave.
9
RO 0x0
Data parity detected
This bit will be set when Bridge detected parity error condition in
data phase
8
RO 0x0
Fast back to back capable
The CardBus bridge doesn’t support fast back to back transactions.
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Version 1.5