HMS30C7110 Datasheet, PDF (141/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
2.13.1.5. Card Status Change Register (CSCR)
Table 2.109 CSCR Bit Definition
Address : 1940_0010
Bits Access Default Description
31:4
0x00 Reserved
3
ROC 0x
Card Detect Change Detected
This bit will be set when a transition (low to high or high to low) has
occurred on the CD2~1 pins. This bit is reset to 0 when this register
is read.
2
ROC 0x0 Ready Change Detected
This bit will be set when a transition (low to high or high to low) has
occurred on the READY pin. This bit is reset to 0 when this register
is read.
This bit has meaning only when the socket is configured for the
memory-only interface. In the I/O and memory interface it reads
back as 0.
1
0x0 Reserved
0
ROC 0x0 Status Change Detected
This bit will be set when a transition (low to high or high to low) has
occurred on the STSCHG pin. This bit is reset to 0 when this register
is read.
2.13.1.6. Interrupt Enable Register (IER)
Table 2.110 IER Bit Definition
Bits Access Default Description
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141
Address : 1940_0014
Version 1.5