HMS30C7110 Datasheet, PDF (106/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
31:6
5
RO
4
RO
3:2
1
RO
0
RO
0x00
0x0
0x0
0x00
0x0
0x0
Reserved
DSR#
This bit is the complement of the Data Set Ready input. In the
loopback mode, this bit is equivalent to DTR in MCR.
CTS#
This bit is the complement of the Clear to Send input. In the
loopback mode, this bit is equivalent to RTS in MCR.
Reserved
DDSR
This bit is the Delta Data Set Ready indicator. It indicates that the
DSR# input to the chip has changed state since the last time it was
read by the CPU.
DCTS
This bit is the Delta Clear to Send indicator. It indicates that the
CTS# input to the chip has changed stat since the last time it was
read by the CPU.
2.7.2.10. Divisor Latch LSB Register (DLL)
The UART contains a programmable Baud Generator. The output frequency of the Baud Generator
is 16 × the divisor number. The output of Baud Generator drives the transmitter and receiver
sections of the associated serial channel. This register contains the lower byte of the divisor number.
DLL is accessible only when LCR bit-7 is set to 1.
Table 2.66 DLL Bit Definition
Bits Access Default Description
31:8
0x00 Reserved.
7: 0 WO 0x00 Lower byte of Divisor number
Address : 1800_0000
2.7.2.11. Divisor Latch MSB Register (DLM)
This register contains the higher byte of the divisor number. DLM is accessible only when LCR bit-
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