HMS30C7110 Datasheet, PDF (109/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
2.8.1.1. Clock Selection
This register contains clock division values (pre-scalar) for 3 channels.
Table 2.69 Clock Selection Register Bit Definition
Bits Access Default Description
31:10
Reserved
9: 8 RW 0
Clock Select for Timer 2
0 = System Bus Clock
1 = System Bus Clock ÷ 4
2 = System Bus Clock ÷ 8
3 = System Bus Clock ÷ 256
7: 6
Reserved
5: 4 RW 0
Clock Select for Timer 1
0 = System Bus Clock
1 = System Bus Clock ÷ 4
2 = System Bus Clock ÷ 8
3 = System Bus Clock ÷ 256
3: 2
Reserved
1: 0 RW 0
Clock Select for Timer 0
0 = System Bus Clock
1 = System Bus Clock ÷ 4
2 = System Bus Clock ÷ 8
3 = System Bus Clock ÷ 256
Address : 1810_0000
2.8.1.2. Timer Control
This register includes timer enable and clear bits for 3 channels.
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