HMS30C7110 Datasheet, PDF (42/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
2.2. Cache
This section describes the cache system of HMS30C7110®.
2.2.1. Architecture
The cache of HMS30C7110® has the following characteristics.
1. 4K byte unified (data + instruction)
2. 4-way set associative
3. 64 sets
4. Write back policy
5. Read miss line fill up
6. 8 words depth write buffer
This cache uses “write back policy” for high performance in write accesses to cacheable area. To
ensure the memory consistency between cache and main memory it supports user controllable line
flush mechanism. The 8 word-depth write-buffer is used to further boost up the performance.
The bit position 31 of address (most significant bit) determines whether the access is cacheable or
non-cacheable. Value of 0 at the 31^st address bit (0x00000000H to 0x0fffffffH) is for cacheable area,
while 1 (0x10000000H to 0x1fffffffH) is for non-cacheable area.
The write buffer receives and keeps write accesses to cacheable/non-cacheable area and performs
actual memory accesses when the bus is idle, program flow (dependency) forces, or user forces.
Accesses to cacheable/non-cacheable area originally do not go into write buffer, i.e., directly go to
main memory. However, user can change this by programming user controllable registers.
2.2.2. User Accessible Registers (Base = 0x1950_0000)
There is one 32bit register to control the cache and write buffer operations (offset = 0x0).
Table 2.6 Cache and Write Buffer Control Register
Bits Access Default Description
31:20 RW 0x0 Reserved and should be set to 0.
19 RW 0x0 This bit controls Burst Selection.
Address : 1950_0000
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