HMS30C7110 Datasheet, PDF (124/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

S_ADDR
HMS30C7110
[29:0] These bits are the base address (start address) of source data to transfer
2.11.1.2. DMA INITIAL DESTINATION REGISTER (DIDST, offset = 0x04, 0x24)
Table 2.92 DMA Initial Destination Register
Field Name
LOC
INC
S_ADDR
Bit
[31]
[30]
[29:0]
DMA0 Address : 1910_0004
DMA1 Address : 1910_0024
Description
Bit 31 is used to select the location of destination.
0: the destination is in the system bus,
1: the destination is in the peripheral bus
Bit 30 is used to select the address increment.
0 = Increment 1= Fixed
These bits are the base address (start address) of destination to transfer
2.11.1.3. DMA CONTROL REGISTER (DCON, offset = 0x08, 0x28)
Field Name Bit
DMD_HS [30]
SYNC.
[29]
INT
[28]
Table 2.93 DMA Control Register
DMA0 Address : 1910_0008
DMA1 Address : 1910_0028
Description
Select one between demand mode and handshake mode.
0 : demand mode is selected
1 : handshake mode is selected.
Select DREQ/DACK synchronization
0: DREQ and DACK are synchronized to PCLK.
1: DREQ and DACK are synchronized to HCLK.
Enable/Disable the interrupt setting for TC(terminal count)
0: TC interrupt is disabled.
1: Interrupt is generated when all the transfer is done.
© 2003 MagnaChip Semiconductor Ltd. All Rights Reserved
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