HMS30C7110 Datasheet, PDF (72/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
MAC_ADDR_31 0x6C 32 RW MAC address 3 (Least significant 4 bytes)
MAC_ADDR_40 0x70 32 RW MAC address 4 (Most significant 2 bytes)
MAC_ADDR_41 0x74 32 RW MAC address 4 (Least significant 4 bytes)
MAC_ADDR_50 0x78 32 RW MAC address 5 (Most significant 2 bytes)
MAC_ADDR_51 0x7C 32 RW MAC address 5 (Least significant 4 bytes)
MAC_ADDR_60 0x80 32 RW MAC address 6 (Most significant 2 bytes)
MAC_ADDR_61 0x84 32 RW MAC address 6 (Least significant 4 bytes)
MAC_ADDR_70 0x88 32 RW MAC address 7 (Most significant 2 bytes)
MAC_ADDR_71 0x8C 32 RW MAC address 7 (Least significant 4 bytes)
P_FRM_ADDR_0 0x90 32 RW Pause frame address (Most significant 2 bytes)
P_FRM_ADDR_1 0x94 32 RW Pause frame address (Least significant 4 bytes)
P_FRM_ID
0x98 32 RW Pause frame Type / Op. code
P_FRM_VALUE 0x9C 32 RW Pause frame delay value
H_TX_BADDR 0xA0 32 RW High priority queue TX address
H_TX_LENGTH 0xA4 32 RW High priority queue TX length
TX_BUF_LVL_L 0xA8 32 RO
TX queue buffer level
TX_ADDR_BK_L 0xAC 32
RO
TX address return
TX_BUF_LVL_H 0xB0 32
RO
TX high priority queue buffer level
TX_ADDR_BK_H 0xB4 32
RO
TX high priority queue address back buffer
level
RX_TIMER
0xB8 32 RW RX timer register
RX_LEVEL
0xBC 32 RW RX level register
TX_TIMER
0xC0 32 RW TX timer register
TX_LEVEL_H
0xC4 32
RW
TX level register High
TX_LEVEL_L
0xC8 32 RO
TX level register Low
2.6.2.1. MAC_MODE (offset = 0x00)
This register defines general operation mode of the Ethernet MAC.
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Version 1.5