HMS30C7110 Datasheet, PDF (54/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
Table 2.13 Registers for ROM controller
Name
Configuration 0
Configuration 1
Configuration 2
Address Width
0x00 32
0x04 32
0x08 32
Access
RW
RW
RW
Description
Timing configuration of bank 0
Timing configuration of bank 1
Timing configuration of bank 2
2.4.2.1. Configuration 0~3
These registers include timing information for all banks.
Table 2.14 Configuration Registers Bit Definition
Address : 1900_0000, 1900_0004, 1900_0008
Bits Access Default Description
31:30
0
Reserved
29:28 RW 0
BUS MODE
00 = A/D non-mux style
01 = A/D mux Intel style
10 = A/D mux, Motorola style
11 = Reserved
27 RW 0
WAIT ENABLE
This 1 bit field accepts/denies the external wait (GPIO2/Wait) signal pin
expending the access time.
0 = disable
1 = enable
26 RW 0
This bit selects the active level of wait signal, which would be connected
to GPIO2/Wait on pin 206. Each setting for each Configuration register
affect only on assigned address range.
0 = active low input
1 = active high input
25:24 RW 0x3 DATA BUS WIDTH
00 = 8 bit wide bus
01 = 16 bit wide bus
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