HMS30C7110 Datasheet, PDF (84/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

15:8 RW 0
7:5 RW 0
4
RW 0
3
RW 0
2:0 RW 0
HMS30C7110
Preamble of RX packet should be byte alligned. All packets with any
number of byte alligned preambles can be received as valid packets.
Reserved
Pause Frame Slot Request ( [7] & ([6] | [5]) )
Need more information to describe this field.
Reserved
TX_PAUSE Enable
0 = Disable TX Pause frame
1 = Enable TX Pause frame.
Reserved
2.6.2.13. MII_MODE (offset = 0x30)
MII_MODE register defines various operation modes of Media Independent Interface.
Table 2.35 MII Mode Register Bit Definition
MAC0 Address : 1920_0030
MAC1 Address : 1920_1030
Bits Access Default Description
31:28
0
Reserved
27:24 RW 0
Additional output delay on TX_EN, TX_ER, and TX_D[3:0].
0x0 = 0ns
0x1 = 1ns
….
0xE = 14ns
0xF = 15ns
23:20 RW 0xF Inter-Transaction gap
This specifies time gap (in MDC cycles) between two consecutive MII
transactions when SCAN mode. Ignored when any mode other than
scan.
0x0 = Reserved
© 2003 MagnaChip Semiconductor Ltd. All Rights Reserved
84
Version 1.5