HMS30C7110 Datasheet, PDF (98/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
Table 2.55 RHR Bit Definition
Address : 1800_0000
Bits Access Default Description
31:8
0x00 Reserved.
7: 0 RO 0x00 RECEIVE DATA
This 8 bit field is loaded with receive data. The receive data is stored in
FIFO. RHR has the byte data first loaded in the FIFO.
2.7.2.2. Transmitter Buffer Register (THR)
This register contains the data byte to be transmitted. The transmit buffer is double buffered,
utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format.
This shift register is loaded from the Transmit Buffer when the transmission of the previous byte is
complete.
Table 2.56 THR Bit Definition
Address : 1800_0000
Bits Access Default Description
31:8
0x00 Reserved.
7: 0 WO 0x00 TRANSMIT DATA
This 8 bit field is loaded with transmit data. The transmit data is double
buffered. THR is copied to transmit shift register to convert serial data.
2.7.2.3. Interrupt Enable Register (IER)
This register enables five types of interrupts for the associated serial channel. Each interrupt can
activate the interrupt request signal. It is possible to totally disable the interrupt system by resetting
bits 0 through 3 of the Interrupt Enable Register (IER). Similarly, setting bits of the IER register to
logic 1, enables the selected interrupt. Disabling an interrupt prevents it from being indicated as
active in the IIR and from activating IRQ signal.
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