HMS30C7110 Datasheet, PDF (59/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
write access, ‘RO’ for read only access. A ‘C’ appended to ‘RW’ or ‘RO’, indicates that some or all
of the bits can be cleared after a write ‘1’ in corresponding bit.
Table 2.15 Registers for SDRAM controller
Name
Configuration
Reserved
Reserved
Reserved
Timing
Refresh Interval
Init control
Address Map
Address Width
0x00 32
0x04 32
0x08 32
0x0C 32
0x10 32
0x14 32
0x18 32
0x1c 32
Access
RW
RW
RW
RW
RW
Description
SDRAM Configuration
Reserved
Reserved
Reserved
SDRAM timing parameters
Refresh interval value & MCLK Timing
Initialize start register
Select address area (Flash or SDRAM)
2.5.2.1. Configuration
These registers include the information of memory size of each bank.
Table 2.16 Configuration register
Bits Access Default Description
31:22
0x0 Reserved
21:20 RW 0x0 ROW WIDTH
00 = 10-bit row width
01 = 11-bit row width
10 = 12-bit row width
11 = 13-bit row width
19:18
0x0 Reserved
17:16 RW 0x0 COLUMN WIDTH
00 = 8-bit column width
01 = 9-bit column width
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