HMS30C7110 Datasheet, PDF (135/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

ARB_MODE6 6
ARB_MODE5 5
ARB_MODE4 4
ARB_MODE3 3
ARB_MODE2 2
ARB_MODE1 1
ARB_MODE0 0
HMS30C7110
00 = REQ 1-2-3-4 01 = REQ 2-3-4-1
10 = REQ 3-4-1-2 11 = REQ 4-1-2-3
Arbiter 6 rotate enable
1
0 = Priority does not rotate, 1 = Priority rotate enable
Arbiter 5 rotate enable
1
0 = Priority does not rotate, 1 = Priority rotate enable
Arbiter 4 rotate enable
1
0 = Priority does not rotate, 1 = Priority rotate enable
Arbiter 3 rotate enable
1
0 = Priority does not rotate, 1 = Priority rotate enable
Arbiter 2 rotate enable
1
0 = Priority does not rotate, 1 = Priority rotate enable
Arbiter 1 rotate enable
1
0 = Priority does not rotate, 1 = Priority rotate enable
Arbiter 0 rotate enable
1
0 = Priority does not rotate, 1 = Priority rotate enable
2.12.1.5. INTERRUPT PENDING REGISTER (INTPND, offset = 0x10)
Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt
request is the highest priority one that is unmasked and waits for the interrupt to be serviced. Since
INTPND is located after the priority logic, only one bit can be set to 1 at most, and that is the very
interrupt request generating IRQ to CPU. In interrupt service routine for IRQ, you can read this
register to determine the interrupt source to be serviced among 23 sources.
Like the SRCPND, this register has to be cleared in the interrupt service routine. We can clear a
specific bit of INTPND register by writing a data to this register. It clears only the bit positions of
INTPND corresponding to those set to one in the data. The bit positions corresponding to those that
are set to 0 in the data remains as they are with no change.
Table 2.101 Interrupt Pending Register
Address : 1930_0010
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