HMS30C7110 Datasheet, PDF (91/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

2.6.2.23. P_FRM_ADDR_1 (offset = 0x94)
HMS30C7110
Table 2.45 Pause Frame Address 1
MAC0 Address : 1920_0094
MAC1 Address : 1920_1094
Bits Access Default Description
31:24 RW 0xC2 Byte 3 of the Pause Frame Multicast address
23:16 RW 0x00 Byte 2 of the Pause Frame Multicast address
15:8 RW 0x01 Byte 1 of the Pause Frame Multicast address
7:0 RW 0x80 Byte 0 of the Pause Frame Multicast address
2.6.2.24. P_FRM_ID (offset = 0x98)
This register holds frame type identifier and operation code of Pause frame.
Table 2.46 Pause Frame Type ID and OP Code
Bits Access Default Description
31:16 RW 0x8808 Type identifier for pause frame
15:0 RW 0x0001 Operation code for pause frame
MAC0 Address : 1920_0098
MAC1 Address : 1920_1098
2.6.2.25. P_FRM_VALUE (offset = 0x9C)
This register holds delay information of Pause frame. This field specifies the number of delay
cycles to pause TX based on MAC_CLK, i.e., 25MHz for 100Mbps and 2.5 MHz for 10Mbps.
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