HMS30C7110 Datasheet, PDF (58/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
path) using state information of main state machine.
The refresh block makes bus request signal to system bus arbiter to start refresh operation and when
the system bus arbiter gives bus grant signal to SDRAM controller, the main control logic detects
this signal and makes refresh command to signal generator.
The data-path block makes DATAOUT signal using system write data bus and makes system read
data bus using DATAIN signal according to state signal. In write operation, the data-path block
asserts the direction signal to enable output path of data pads.
SYSTEM BUS
CONFIGRUATION
REGISTERS
MAIN CONTROL
LOGIC
ADDRESS CONTROL
SIGNALS
GENERATOR
ADDR
nSCS
nRAS
nCAS
DQM
nSWE
REFRESH
CONTROLLER
DATA PATH
DATA
Figure 2.5 Block Diagram of SDRAM controller
2.5.2. User Accessible Registers (Base = 0x1908_0000)
This section describes all base, control and status register inside the SDRAM controller. The
address field indicates a relative address in hexadecimal. Width specifies the number of bits in the
register and access specifies the valid access types that register. Where ‘RW’ stands for read and
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