HMS30C7110 Datasheet, PDF (68/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
address, then CRC will be calculated over 48-bit destination address, and 5 most significant bits are
used to locate one of 64 bits of the multicast address register. If the bit to be pointed by the 5 most
significant bits is set, then the frame will be received. With sufficient number of bytes held in the
System Receive FIFO, the DMA engine will start transfer the stored frame to the system memory
space that is pre-programmed by the CPU. An interrupt will be asserted to notify that a frame
transfer is completed and the CPU should write the start address of the next buffer for the next
incoming frame.
In transmit operation, the CPU prepares a frame and notify the MAC that a frame is ready to
transfer. The MAC DMA engine moves the frame from the system memory to System Transmit
FIFO. When the state machine detects there is a frame being stored in the System Transmit FIFO
and that carrier sense is not detected, the frame will be transferred. Pad byte (0x00) may be inserted
if required, and CRC will be appended at the end of the frame. Preamble will be added before the
frame, jam signaling will be asserted when collision occurs. The data stream will be either serialized
for the 7-wire interface or converted to nibbles/bi-bits for MII/RMII.
D
M
Frame
Mux
A
-
S
CONFIG
Y
S
T
STATUS
E
M
B
U
SyS
S
RX
FIFO
SYS
TX
FIFO
CRC ADDR
FIFO CTRL
FIFO
CTRL
Pad Insert / Mux
P
H
Y
I
CRC
/
F
TIMER
-
(R)
M
I
MAC
RX
FIFO
SFD
Check
I
Figure 2.9 Block Diagram of Ethernet MAC
© 2003 MagnaChip Semiconductor Ltd. All Rights Reserved
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Version 1.5