HMS30C7110 Datasheet, PDF (65/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
2.5.3.3. Initialization
Table 2.21 Initialization Sequence
Sequence
SDRAM requirement
Comments
1
Apply power and start clock
MCLK operates during RESET period
2
Maintain stable power and clock Power on reset normally takes longer than 1 ms
for at least 1 ms
3
NOP command (optional)
Software asserts NOP command using command register
4
Waiting for min 200 us
Software waits for 200 us using for-loop or while-loop
5
Software sets valid values in Timing registers
6
Software sets the refresh interval
7
Pre-charge all banks of all blocks Software sets the init bit of command register
8
Perform 20 times refresh cycles
9
Program SDRAM mode register
10
Polling the init bit and if init bit is cleared, then initialization is finish
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