HMS30C7110 Datasheet, PDF (50/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
11 : 100MHz – 160MHz
1
RW 0x0
vcoinit : VCO initialize signal
During power-up sequence, vcoinit is recommended to be activated for
more than 100ns just after deactivation of the vcopd signal.
0
RW 0x0
vcopd : VCO power down mode
If set to “1”, PLL will not generate clock and VCO will stop.
Fck = Fref × (m+2) / (n + 1)
2.3.2.5. PLL Status
This register controls Software reset of PLL and some of control signals of PLL module and
indicates PLL locking status.
Table 2.12 PLL Status
Address : 1830_0010
Bits Access Default Description
31 RW 0x0 BYPASS, PLL bypass mode “active high”
30 RW 0x0 Cnttest, PLL counter toggle test “active high”
29 RW 0x0 Lfo, PLL External loop filter port “ analog”
28:25 RW 0xa ICP, PLL charge pump bias current control vector
24 RW 0x0 Tdm, PLL digital part test mode “active high”
23:22 RW 0x0 Tpdud, PLL charge pump test mode (Normal mode ‘00’)
21:5
0x0 Reserved
4
RW 0x0
PLL Software RESET “active high”
3:1
0x0 Reserved
0
R
0x0 Main PLL locking end: high active
Refer MAGNACHIP PLL User guide
© 2003 MagnaChip Semiconductor Ltd. All Rights Reserved
50
Version 1.5