HMS30C7110 Datasheet, PDF (73/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
Table 2.23 MAC Mode Register Bit Definition
MAC0 Address : 1920_0000
MAC1 Address : 1920_1000
Bits Access Default Description
31 RW 0
UNICAST_ENABLE
0 = Disable receiving unicast frames
1 = Enable receiving unicast frames
30 RW 0
MULTICAST_ENABLE
0 = Disable receiving multicast frames
1 = Enable receiving multicast frames
29 RW 0
BROADCAST_ENABLE
0 = Disable receiving broadcast frames
1 = Enable receiving broadcast frames
28 RW 0
RECEIVE_ALL_ENABLE
0 = Frames will be received based on Bits [31:29].
1 = Enable receiving all frames.
When “1”, if any MAC address is set to be valid, the frame with valid
MAC address will be dropped (see valid bit of MAC address registers).
27:19
0
Reserved
18 RW 0
TX Error signaling
0 = LOW output at TX_ER pin for error signaling
1 = HIGH output at TX_ER pin for error signaling
17 RW 1
TX data valid polarity
0 = active low data valid output to PHY
1 = active high data valid output to PHY
16 RW 0
TX_EN
0 = Disable TX after the current frame is transmitted
1 = Enable TX
15:11
0
Reserved
10 RW 1
RX Error polarity
0 = active low error output to PHY
1 = active high error output to PHY
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