HMS30C7110 Datasheet, PDF (8/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
Table 2.29 Transmit Buffer Length............................................................................ 81
Table 2.30 Receive Buffer Address ........................................................................... 81
Table 2.31 Receive Frame Status............................................................................... 82
Table 2.32 Receive Buffer Level................................................................................ 82
Table 2.33 RX Address Return ................................................................................... 83
Table 2.34 Control Mode Register Bit Definition ...................................................... 83
Table 2.35 MII Mode Register Bit Definition ............................................................. 84
Table 2.36 MII Command Register Definition ............................................................ 85
Table 2.37 MII Transmit Data Register...................................................................... 87
Table 2.38 MII Receive Data Register ....................................................................... 87
Table 2.39 Length Register ........................................................................................ 87
Table 2.40 Multicast Address (Most Significant) ...................................................... 88
Table 2.41 Multicast Address (Least Significant) ..................................................... 88
Table 2.42 MAC Address 0 (Control & Byte 5, 4) .................................................... 89
Table 2.43 MAC Address 1 (Byte 3, 2, 1, 0) ............................................................. 89
Table 2.44 Pause Frame Address 0 ........................................................................... 90
Table 2.45 Pause Frame Address 1 ........................................................................... 91
Table 2.46 Pause Frame Type ID and OP Code ........................................................ 91
Table 2.47 Pause frame delay value .......................................................................... 92
Table 2.48 TX High Priority Queue Base Address.................................................... 92
Table 2.49 TX High Priority Queue Length ............................................................... 92
Table 2.50 TX Low Priority Queue Level .................................................................. 93
Table 2.51 TX Low Priority Queue Address Return ................................................. 93
Table 2.52 TX High Priority Queue Level ................................................................. 94
Table 2.53 TX High Priority Queue Address Return................................................. 94
Table 2.54 Registers for UART .................................................................................. 97
Table 2.55 RHR Bit Definition..................................................................................... 98
Table 2.56 THR Bit Definition .................................................................................... 98
Table 2.57 IER Bit Definition ...................................................................................... 99
Table 2.58 IIR Bit Definition ....................................................................................... 99
Table 2.59 Interrupt Control Functions.................................................................... 100
Table 2.60 FCR Bit Definition ................................................................................... 101
Table 2.61 LCR Bit Definition ................................................................................... 102
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