HMS30C7110 Datasheet, PDF (79/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

4
RW 0
3
RW 0
2
RW 0
1
RW 0
0
RW 0
1 = Interrupt enabled
RX completed
0 = Interrupt disabled
1 = Interrupt enabled
SYS RX FIFO overflow.
0 = Interrupt disabled
1 = Interrupt enabled
SYS RX FIFO underflow.
0 = Interrupt disabled
1 = Interrupt enabled
MAC RX FIFO overflow
0 = Interrupt disabled
1 = Interrupt enabled
MAC RX FIFO underflow.
0 = Interrupt disabled
1 = Interrupt enabled
HMS30C7110
2.6.2.4. IF_GAP (offset = 0x0C)
This register defines a gap time between two back-to-back frames.
Table 2.26 Inter-Frame Gap Register
MAC0 Address : 1920_000C
MAC1 Address : 1920_100C
Bits Access Default Description
31:7
0
Reserved
6:0 RW 0x18 Back to Back Inter Packet Gap
The recommended value is 0x0C (24 – 12 = 12) for MII, 0x54 (96 – 12
= 84) for 7-wire interface, which equals to 0.96us (100Mbps) or 9.6us
(10Mbps).
© 2003 MagnaChip Semiconductor Ltd. All Rights Reserved
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