HMS30C7110 Datasheet, PDF (108/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

2.8. TIMER
HMS30C7110
The HMS30C7110® integrates 3 channels of Timers and each channel has 32-bit down counter. The
input clock of each channel is selectable among one of the 4 clock speeds, System Bus Clock/1,
System Bus Clock/4, System Bus Clock/16, or System Bus Clock/256. When the clock of the
system bus is 100MHz, the Timer input options are 100/25/6.25/0.4MHz. When the clock of the
system is 80MHz, the Timer input options are 80/20/5/0.3125MHz. The Timers are fully
configurable through a set of control registers. Complete descriptions of these registers are given in
the Register Section.
2.8.1. User Accessible Registers (Base = 0x1810_0000)
This section describes all base, control and status registers inside the Timer. The address field
indicates a relative address in hexadecimal. Width specifies the number of bits in the register and
access specifies the valid access types that register. Where ‘RW’ stands for read and write access,
‘RO’ for read only access. A ‘C’ appended to ‘RW’ or ‘RO’, indicates that some or all of the bits can
be cleared after a write ‘1’ in corresponding bit.
Table 2.68 Registers for TIMER
Name
Clock Selection
Timer Control
Timer Interval 0
Timer Interval 1
Timer Interval 2
Timer Value 0
Timer Value 1
Timer Value 2
INT SRC
INT ENABLE
Address Width
0x00 3x2
0x04 3x2
0x08 32
0x0c 32
0x10 32
0x14 32
0x18 32
0x1c 32
0x20 3
0x24 3
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Description
Input clock selection for 3 channels
Channel enable/disable
Reload value for Timer Channel 0
Reload value for Timer Channel 1
Reload value for Timer Channel 2
Channel 0 current timer value
Channel 1 current timer value
Channel 2 current timer value
Interrupt pending register
Interrupt enable register
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