HMS30C7110 Datasheet, PDF (97/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
2.7.2. User Accessible Registers (Base = 0x1800_0000)
This section describes all base, control and status register inside the UART. The address field
indicates a relative address in hexadecimal. The base address of UART0 is 0x18000000 and UART1
is 0x18080000. Only UART1 has a hardware flow control. Width specifies the number of bits in the
register and access specifies the valid access types that register. Where RW stands for read and write
access, RO for read only access. A “C” appended to RW or RO, indicates that some or all of the bits
can be cleared after a write ‘1’ in corresponding bit. Base address for UART 1 is 0x1808_0000.
Name
RHR
THR
IER
IIR
FCR
LCR
MCR
LSR
MSR
DLL
DLM
Table 2.54 Registers for UART
Address Width
0x00 8
0x00 8
0x04 4
0x08 4
0x08 2
0x0c 7
0x10 4
0x14 8
0x18 8
0x00 8
0x04 8
Access
RO
WO
RW
RO
WO
RW
RW
RO
RO
WO
WO
Description
Receiver Holding Register
Transmitter Holding Register
Interrupt Enable Register
Interrupt Identification Register
FIFO Control Register
Line Control Register
MODEM Control Register
Line Status Register
MODEM Status Register
Divisor Latch LSB Register
Divisor Latch MSB Register
*DLL and DLM are accessible ONLY when LCR bit-7 is set to “1”
2.7.2.1. Receiver Holding Register (RHR)
This register holds the received incoming data byte. Bit 0 is the least significant bit, which is
transmitted and received first. Received data is double buffered; this uses an additional shift register
to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the
Receive Buffer register. The shift register is not accessible.
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