HMS30C7110 Datasheet, PDF (130/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

INT_EXT0
HMS30C7110
0
External interrupt 0 (from GPIO0)
ARB0
Arbitration block
The priority logic for 32 interrupt requests is composed of seven rotation based arbiters: six first-
level arbiters and one second-level arbiter as shown in the following figure.
REQ0
REQ1
IRQ
ARB6
REQ2
REQ3
REQ4
REQ5
ARB0
ARB1
ARB2
ARB3
ARB4
REQ1: INT_EXT0
REQ2: INT_EXT1
REQ3: INT_EXT2
REQ4: INT_EXT3
REQ0: INT_EXT4
REQ1: INT_EXT5
REQ2: INT_EXT6
REQ3: INT_EXT7
REQ4: Reserved
REQ5: Reserved
REQ0: INT_TIMER
REQ1: INT_ENET0
REQ2: Reserved
REQ3: Reserved
REQ4: INT_ENET1
REQ5: Reserved
REQ0: Reserved
REQ1: INT_DMA0
REQ2: INT_DMA1
REQ3: INT_GPIO
REQ4: INT_PCMCIA
REQ5: INT_PCMIRQ
REQ0: INT_CARDBUS
REQ1: Reserved
REQ2: Reserved
REQ3: Reserved
REQ4: INT_I2C
REQ5: INT_SPI
ARB5
REQ1: INT_UART0
REQ2: INT_UART1
REQ3: Reserved
REQ4: Reserved
Figure 2.12 Arbitration Block Diagram
Each arbiter can handle six interrupt requests based on the one bit arbiter mode control
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