HMS30C7110 Datasheet, PDF (75/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

2.6.2.2. INT_SRC (offset = 0x04)
The Ethernet MAC provides 30 interrupt sources.
HMS30C7110
Table 2.24 Interrupt Source Bit Definition
MAC0 Address : 1920_0004
MAC1 Address : 1920_1004
Bits Access Default Description (Write “1” to clear each bit)
31 RW 0
1 = MII PHY interrupt
30 RW 0
1 = MII Scan interrupt
29 RW 0
1 = TX error at PHY
28 RW 0
1 = RX error at PHY
27 RW 0
1 = TX address return buffer overflow.
26 RW 0
1 = TX address return buffer underflow
25 RW 0
1 = Collision Detected
24 RW 0
1 = Carrier Sense Detected
23
0
Reserved.
22 RW 0
1 = TX complete (high priority queue)
21 RW 0
1 = Late collision detected
20 RW 0
1 = TX completed (low priority queue)
19 RW 0
1 = SYS TX FIFO overflow
18 RW 0
1 = SYS TX FIFO underflow
17 RW 0
1 = MAC TX FIFO overflow
16 RW 0
1 = MAC TX FIFO underflow
15 RW 0
1 = TX length buffer overflow (low priority queue)
14 RW 0
1 = TX length buffer underflow (low priority queue)
13 RW 0
1 = TX address buffer overflow (low priority queue)
12 RW 0
1 = TX address buffer underflow (low priority queue)
11 RW 0
1 = RX status buffer overflow
10 RW 0
1 = RX status buffer underflow
9
RW 0
1 = RX address buffer overflow
8
RW 0
1 = RX address buffer underflow
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