HMS30C7110 Datasheet, PDF (121/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
Table 2.86 Tx Data Register Bit Definition
Bits Access Default Description
31:8
0
Reserved
7:0 RW 0
Tx Data
Address : 1840_0018
2.10.2.4. RX Data (offset = 0x20)
This register is reading path of 32 bytes Rx FIFO.
Table 2.87 Rx Data Register Bit Definition
Bits Access Default Description
31:8
0
Reserved
7: 0 RW 0
Rx Data
Address : 1840_001C
2.10.2.5. INT SRC
This register includes SPI interrupt source bits.
Table 2.88 Interrupt Source Register Bit Definition
Bits Access Default Description
31: 1
0
Reserved
0
RW 0
TX done
Address : 1840_0020
2.10.2.6. INT ENABLE
This register includes SPI interrupt enable bits.
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