HMS30C7110 Datasheet, PDF (85/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
19:18
0
17 RW 1
16 RW 1
15:8 RW 0x64
7:1
0
0
RWC 0
0x1 = (number of gap cycle = 1)
0x2 = (number of gap cycles = 2)
…
0xE = (number of gap cycles = 14),
0xF= (number of gap cycles = 15)
Reserved
Preamble
0 = No MII preamble will be used.
1 = 32-bit preamble will lead MII transaction.
MDC Mode
0 = Gated MDC
1 = Continuous MDC
Clock Divider
This field defines a host cock divider factor. The host clock can be
divided by an even number, greater than 1. The default value is 0x64
(100 in decimal).
Reserved
MII Reset
0 = Normal operation
1 = Reset active (auto-clear after reset is done)
2.6.2.14. MII_CMD (offset = 0x34)
This register defines command operation of MII
Table 2.36 MII Command Register Definition
Bits Access Default Description
31:24
0
Reserved
23:19
0
Reserved
MAC0 Address : 1920_0034
MAC1 Address : 1920_1034
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