HMS30C7110 Datasheet, PDF (52/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

2.4. Memory Controller (Flash/ROM)
HMS30C7110
The HMS30C7110® has integrated External Bus controller that supports 8-bit/16-bit/32-bit data
bus width. The space is divided into 3 static memory (FLASH/ROM) banks. Each bank has fixed
size of 4MB. The operating clock of external bus controller is the internal system bus clock. The
bus timing exclusively depends on the register programming. The external bus controller is fully
configurable through a set of control register. Complete descriptions of these registers are given in
the Register Section.
The twenty-two address lines, RA [21:0], allow HMS30C7110® to support up to 1M×32 bit,
2Mx16 bit, or 4Mx8 bit space. Three nRCS lines make three times bigger space.
Each block can be configured independently for the bus style, the wait enable, the shaping of bus
control signal.
2.4.1. Block Diagram
The external bus controller of HMS30C7110® consists of several blocks such as main state
machine, register file, data-path, signal generator and address generator.
Commands fed via system bus are interpreted in the main state machine and the main state machine
generates control signals to all of the signal generation blocks (address generator, signal generator
and data-path) using the state signal.
The data-path block makes DATAOUT signal using HWDATA and makes HRDATA using DATAIN
signal according to state signal. In write operation, the data-path block asserts the direction signal to
enable output path of data pads. The signal generator makes nRCS, nOE, and nWE.
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