HMS30C7110 Datasheet, PDF (37/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
BLOCK
ROM
Controller
SDRAM
Controller
DMA
Controller
Table 2.5 Register Map at AMBA Host-Bus
ADDRESS NAME
1900_0000 ROM Timing Control for Bank 0
_0004 ROM Timing Control for Bank 1
_0008 ROM Timing Control for Bank 2
0000c – 7fffc RESERVED
1908_0000 SDRAM Configuration
_0004 Reserved
_0008 Reserved
_000c Reserved
_0010 SDRAM timing parameters
_0014 Refresh interval value & MCLK timing
_0018 Initialize start register
_001c Booting Control Register
80020 – 7fffc RESERVED
1910_0000 DMA Initial Source Register for channel 0
_0004 DMA Initial Destination Register for CH0
_0008 DMA Control Register for CH0
_000c DMA Status Register for CH0
_0010 DMA Current Source Register for CH0
_0014 DMA Current Destination Register for CH0
_0018 DMA Mask Trigger Register for CH0
_001c Reserved
_0020 DMA Initial Source Register for channel 1
_0024 DMA Initial Destination Register for CH 1
_0028 DMA Control Register for CH 1
_002c DMA Status Register for CH 1
_0030 DMA Current Source Register for CH 1
_0034 DMA Current Destination Register for CH 1
_0038 DMA Mask Trigger Register for CH 1
0003c – ffffc RESERVED
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
R
R
R
R/W
© 2003 MagnaChip Semiconductor Ltd. All Rights Reserved
37
Reset Value
0333_00ff
03ff_ffff
03ff_ffff
0000_0000
0000_003f
7777_ff71
1303_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
Version 1.5