HMS30C7110 Datasheet, PDF (92/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
Table 2.47 Pause frame delay value
Bits Access Default Description
31:16
0
Reserved
15:0 RW 0x0018 Delay value
MAC0 Address : 1920_009C
MAC1 Address : 1920_109C
2.6.2.26. H_TX_BADDR (offset = 0xA0)
This register holds base address of a frame to be transmitted via high priority TX queue (single
entry).
Table 2.48 TX High Priority Queue Base Address
MAC0 Address : 1920_00A0
MAC1 Address : 1920_10A0
Bits Access Default Description
31:0 RW 0
Base address of TX frame for high priority queue
2.6.2.27. H_TX_LENGTH (offset = 0xA4)
This register holds length of a frame to be transmitted via high priority TX queue (single entry).
Table 2.49 TX High Priority Queue Length
MAC0 Address : 1920_00A4
MAC1 Address : 1920_10A4
Bits Access Default Description
31:0 R/W 0
Length of TX frame for high priority queue
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