HMS30C7110 Datasheet, PDF (123/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

2.11. DMA
HMS30C7110
HMS30C7110® supports two-channel DMA controller that is located between the system bus and
the peripheral bus. Each channel of DMA controller can perform data movements between devices
in the system bus and/or peripheral bus with no restrictions. In other words, each channel can
handle the following four cases: 1) both source and destination are in the system bus, 2) source is in
the system bus while destination is in the peripheral bus, 3) sources in the peripheral bus while
destination is in the system bus, 4) both source and destination are in the peripheral bus.
The main advantage of DMA is that it can transfer data without any CPU intervention. The
operation of DMA can be initiated by S/W, the request from internal peripherals or the external
request pins.
2.11.1. User Accessible Registers (Base = 0x1910_0000)
There are seven control registers for each DMA channel (Since there are two channels, the total
number of control registers is 14). Four of them are to control the DMA transfer, and other three are
to see the status of DMA controller. The details of those registers for a channel are as follows.
2.11.1.1. DMA INITIAL SOURCE REGISTER (DISRC, offset = 0x00, 0x20)
Field Name Bit
LOC
[31]
INC
[30]
Table 2.91 DMA Initial Source Register
DMA0 Address : 1910_0000
DMA1 Address : 1910_0020
Description
Bit 31 is used to select the location of source.
0: the source is in the system bus,
1: the source is in the peripheral bus
Bit 30 is used to select the address increment.
Increment unit is determined by DS of DCON.
0 = Increment 1= Fixed
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